Satellite OBC Selection Guide (III): Power Requirements-Efficient Operation within Limited Power Consumption

The satellite's power supply depends entirely on solar cells, and its power resources are extremely limited (usually only tens to hundreds of watts). As the core processing unit, OBC's power consumption directly affects the overall endurance and mission execution efficiency of the satellite. Therefore, the balance between "low power consumption" and "high computing power" is the core goal of OBC power requirements.

The core power consumption component of OBC: the choice of FPGA

Among the electronic components of OBC, field programmable gate array (FPGA) is one of the components with the highest power consumption, and its technology selection directly determines the power consumption level of OBC. The following two types of FPGA are preferred:

Flash FPGA: it belongs to "non-volatile" FPGA, and it does not need to be reconfigured every time it is powered on, thus avoiding high current consumption in the configuration process; At the same time, flash FPGA adopts "real-time power-on" technology, which has no surge current peak, can start smoothly and reduce instantaneous power consumption.

Anti-fuse FPGA: It also has the characteristics of "real-time power-on", which has no surge current and strong radiation resistance (suitable for some long-term tasks). However, its disadvantage is one-time programming, unable to modify the configuration later, and low flexibility.

In contrast, the traditional SRAM FPGA needs to consume high configuration current every time it is powered on, and it is easily affected by radiation, which leads to configuration loss. Not only does it consume high power, but it also needs to design an additional "configuration backup" mechanism, which is not suitable for satellite OBC scenarios.

Key strategy of OBC power consumption optimization

In addition to component selection, OBC power consumption can be further reduced by the following strategies:

1. Dynamic computing power adjustment: flexibly adjust the working frequency of the processor and FPGA according to the task stage —— for example, when the satellite is in the "data transmission window", increase the processor frequency to speed up data compression and transmission; In the idle phase (such as orbital cruise), the frequency is reduced to reduce power consumption.
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3. Component sleep mechanism: adopt "sleep mode" for non-core components (such as standby interfaces and redundant modules)-for example, when OBC only needs to process attitude control data, it can turn off the power of the data compression module and wake up when necessary to avoid invalid power consumption.
4. Power consumption budget planning: In the early stage of OBC design, it is necessary to make clear the power consumption budget of each component (such as processor ≤5W and FPGA≤8W), and verify whether the actual power consumption meets the requirements through simulation tools (such as SPICE) to avoid affecting the overall power balance due to excessive power consumption of individual components.
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Practical considerations of power requirements

The power consumption requirements of satellites in different mission stages (such as launch, on-orbit operation and data transmission) are different: for example, OBC needs to work continuously to monitor the state of satellites in the launch stage, and the power consumption is relatively stable; In the data transmission stage, the power consumption will increase temporarily due to the need to process a large amount of data. Therefore, the power module of OBC should have "dynamic power supply capability", which can adjust the output current according to the task load and avoid the fault caused by voltage fluctuation.

In a word, the power requirements of OBC need to focus on "limited power supply": through the accurate selection of core components (FPGA) and the dynamic power consumption optimization strategy, the power consumption can be minimized while meeting the task computing requirements.